This invention relates to data processing systems, and in particular, to the arithmetic logic unit of the data processing systems and even more particularly to a carry look ahead, both forwards and backwards, for an arithmetic logic unit.
A major limitation in the use of field effect transistor circuits and in particular, large scale integrated circuits, is the restriction associated with extending the dynamic logic circuits, such as those found in an arithmetic logic unit, to high speed applications due to the necessity of multiple clocks that are required for the implementation of logic circuits with field effect transistors. An additional limitation is propagation delays associated in the arithmetic logic units that are associated with data processing systems and in particular, with microprocessors, is the delays encountered through the implementation of the carry signals during an addition operation.
The minimization of time in a data processing system such as a microprocessor system that is required to implement a mathematical function in the arithmetic logic unit may be reduced from many processing cycles of the microprocessor to a relatively few number of processing cycles through the implementation of the carry forward and backward arithmetic logic unit as disclosed herein.